搜索资源列表
dft
- verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
lcd-code
- 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
ETH
- 该系统通过顶层模块，调用4底层模块实现。4大模块底层模块为：cpu模块、发送模块、接收模块、mii模块-The system top-level module, called the bottom module 4. 4 large modules underlying module: cpu modules, transmit modules, receiver modules, mii module
class34
- eda中的8位的CPU设计，电子类专业非常实用！-EDA in eight of the CPU design, electronics professional very useful!
8086IP
- 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
vgachr8080
- code guide to design cpu -code guide to design cpu 8080
8080cpu
- this code for cpu 8080 design -this is code for cpu 8080 design
testbenchcpu8080
- this is code testbench cpu -this is code testbench cpu 8080
cam
- Desin 1 simple CPU. important module
ALU
- 这是一个用vhdl语言实现的比较完整的ALU,可以用作其他cPU设计的部件-This is a vhdl language used to achieve complete ALU, can be used for other design components cPU
Jh_cpu
- Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
POCREPORT
- 为充分利用CPU的运行效率，采用中断功能设计并行输入输出接口，以达到缓解CPU高速运行速度与外设低速缓冲间的矛盾。-To take full advantage of the efficiency of CPU operation, interruption of functional design using parallel input-output interface, in order to alleviate the CPU speed and high-speed periphera
first_cpu
- nios ii cpu核，包含通用IO口、sdram、flash、uart-nios ii cpu、genernal io port、sdram、falsh、uart
computer4
- 基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
POC
- 东南大学学生数字系统设计实验：用VHDL语言编写Printer与CPU互连的接口程序-Southeast University students in the experimental digital system design: VHDL language with Printer and CPU interface interconnection procedures
cpudesignvhd
- 内包含在VHDL环境下的CPU设计原理图和代码以及最后的仿真过程-Within the VHDL environment is included in the CPU design schematics and code, as well as the final simulation
dianhuanyuanchengkongzhi
- 电话智能遥控器主要包括电话振铃检测电路，电话自动摘机和挂机电路，DTMF信号解码电路，语音提示急电路，音频放大电路，以及控制心脏CPU电路-Telephone remote control including smart phones ringing detection circuit, telephone and hang up automatically pick circuit, DTMF signal decoding circuit, urgent voice circuits, au
8051-core
- mcu8051 CPU FPGA VHDL software
soc-gr0040-010309
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
lariviere2008uclinux
- xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga